The present invention relates to a semiconductor device, and more particularly, to a recessed gate dielectric antifuse.
A conventional Metal Oxide Semiconductor Field Effect Transistor (MOSFET) comprises a doped polysilicon gate, a channel conduction region, and source/drain regions formed by diffusion of dopants in the silicon substrate. The channel region separates the source from the drain in the lateral direction. A substantially planar layer of a dielectric material that prevents electrical current flow separates the polysilicon gate from the channel. The substantially planar dielectric material separating the polysilicon gate from the channel region, henceforth referred to as the gate oxide, usually consists of the thermally grown silicon dioxide (SiO2) material that leaks very little current through a mechanism, which is called Fowler-Nordheim tunneling under voltage stress.
A reliable, low resistance, programmable antifuse may be formed from such a conventional MOSFET, which provides a high impedance between the gate and the source, the drain, the substrate, or a well. When the MOSFET is stressed beyond a critical electrical field by applying sufficient voltage to the gate, the transistor is destroyed by rupturing the gate oxide. In particular, the gate oxide over the substrate becomes a resistive short, causing part of the gate oxide to form current paths by diffusion of polysilicon gate material or silicon from the substrate.
To increase device yield, semiconductor integrated circuits such as EPROMs, flash EEPROMs, DRAM, SRAM, and other various random access memory types employ redundant circuitry that allows the integrated circuits to function despite the presence of one or more manufacturing or other defects by employing the redundant circuitry rather than the original, defective circuitry. Such conventional memories often use gate-oxide antifuses as part of their redundancy scheme wherein the redundant circuitry may be employed in place of defective circuitry by blowing one or more of the antifuses.
To keep pace with the current trend toward maximizing the number of circuit devices contained in a single chip, integrated circuit designers continue to design IC devices with smaller and smaller feature sizes.